中国机械工程学会生产工程分会知识服务平台

期刊


ISSN0913-5685
刊名電子情報通信学会技術研究報告
参考译名电子信息通信学会技术研究报告：硅器件和材料
收藏年代2000～2024



全部

2000 2001 2002 2009 2013 2014
2015 2017 2020 2021 2022 2023
2024

2001, vol.101, no.107 2001, vol.101, no.108 2001, vol.101, no.246 2001, vol.101, no.247 2001, vol.101, no.320 2001, vol.101, no.321
2001, vol.101, no.350 2001, vol.101, no.430 2001, vol.101, no.515 2001, vol.101, no.571 2001, vol.101, no.573 2001, vol.101, no.718
2001, vol.101, no.719

题名作者出版年年卷期
MPEG-4 video codec LSI: its features and core technologyShun-ichi Kurohmaru; Junji Michiyama20012001, vol.101, no.246
Design of general purpose vision chip with PE blocking functionTakashi Komuro; Masatoshi Ishikawa20012001, vol.101, no.246
One-chip 15-frame/s mega-pixel real-time image processorHideki Yamauchi; Shigeyuki Okada; Kazuhiko Taketa; Yuh Matsuda; Tugio Mori; Tsuyoshi Watanabe; Shin'ichiro Okada; Yoshitaka Ueda; Hiroki Miura; Akio Kobayashi; Naruhito Takada; Yasoo Harada20012001, vol.101, no.246
Search area sizes optimization for "2-step improved breaking-off-search (2S-IBOS)" motion estimation algorithm and low-power 0.13-μm CMOS motion estimators for MPEG4 encodingTomomi Ei; Akira Kotabe; Tomochika Harada; Tadayoshi Enomoto20012001, vol.101, no.246
An image recognition LSI for smart cars implemented using a configurable processorYoshihisa Kondo20012001, vol.101, no.246
A pulse-modulation pixel-parallel Gabor filter circuit for image feature extractionJ. Umezawa; S. Nishijima; M. Miyake; T. Morie; M. Nagata; A. Iwata20012001, vol.101, no.246
A pixel-parallel region extraction algorithm for image recognition and implementation on FPGAT. Nakano; S. Hikomoto; T. Morie; M. Nagata; A. Iwata20012001, vol.101, no.246
High-performance CMOS circuits in sub-100-nm era: issues and solutionsKazuo Yano; Naoki Kato20012001, vol.101, no.246
A low-power SOI adder using reduced swing charge recycling circuitsAtsuki Inoue; William W. Walker; Vojin G. Oklobdzija; Mutsuaki Kai; Tetsuo Izawa20012001, vol.101, no.246
Dynamically controllable DC level converter (DCLC) technique to reduce power dissipation, and application to high-speed, low-power circuitsYoshinori Oka; Hiroaki Shikano; Tomochika Harada; Tadayoshi Enomoto20012001, vol.101, no.246
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